1#pragma once
  2
  3/* SPDX-License-Identifier: MIT */
  4#if __has_include(<drm.h>)
  5    #include <drm.h>
  6#else
  7    #include <drm/drm.h>
  8#endif
  9
 10// xe_drm.h
 11
 12/*
 13 * Copyright © 2023 Intel Corporation
 14 */
 15
 16#define DRM_XE_DEVICE_QUERY 0x00
 17
 18#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
 19
 20enum drm_xe_memory_class {
 21    DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
 22    DRM_XE_MEM_REGION_CLASS_VRAM
 23};
 24
 25struct drm_xe_mem_region {
 26    __u16 mem_class;
 27    __u16 instance;
 28    __u32 min_page_size;
 29    __u64 total_size;
 30    __u64 used;
 31    __u64 cpu_visible_size;
 32    __u64 cpu_visible_used;
 33    __u64 reserved[6];
 34};
 35
 36struct drm_xe_query_mem_regions {
 37    __u32 num_mem_regions;
 38    __u32 pad;
 39    struct drm_xe_mem_region mem_regions[];
 40};
 41
 42struct drm_xe_query_topology_mask {
 43    __u16 gt_id;
 44
 45#define DRM_XE_TOPO_DSS_GEOMETRY 1
 46#define DRM_XE_TOPO_DSS_COMPUTE 2
 47#define DRM_XE_TOPO_EU_PER_DSS 4
 48    __u16 type;
 49    __u32 num_bytes;
 50    __u8 mask[];
 51};
 52
 53struct drm_xe_device_query {
 54    __u64 extensions;
 55
 56#define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
 57#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
 58    __u32 query;
 59    __u32 size;
 60    __u64 data;
 61    __u64 reserved[2];
 62};
 63
 64// i915_drm.h
 65
 66/*
 67 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 68 * All Rights Reserved.
 69 */
 70
 71#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 72
 73struct drm_i915_getparam {
 74    __s32 param;
 75    int* value;
 76};
 77typedef struct drm_i915_getparam drm_i915_getparam_t;
 78
 79#define DRM_I915_GETPARAM 0x06
 80#define DRM_I915_QUERY 0x39
 81#define DRM_I915_QUERY_MEMORY_REGIONS 4
 82#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
 83#define I915_PARAM_EU_TOTAL 34
 84
 85struct drm_i915_query_item {
 86    __u64 query_id;
 87#define DRM_I915_QUERY_MEMORY_REGIONS 4
 88
 89    __s32 length;
 90    __u32 flags;
 91    __u64 data_ptr;
 92};
 93
 94struct drm_i915_query {
 95    __u32 num_items;
 96    __u32 flags;
 97    __u64 items_ptr;
 98};
 99
100enum drm_i915_gem_memory_class {
101    I915_MEMORY_CLASS_SYSTEM = 0,
102    I915_MEMORY_CLASS_DEVICE,
103};
104
105struct drm_i915_gem_memory_class_instance {
106    __u16 memory_class;
107    __u16 memory_instance;
108};
109
110struct drm_i915_memory_region_info {
111    struct drm_i915_gem_memory_class_instance region;
112    __u32 rsvd0;
113    __u64 probed_size;
114    __u64 unallocated_size;
115
116    union {
117        __u64 rsvd1[8];
118        struct {
119            __u64 probed_cpu_visible_size;
120            __u64 unallocated_cpu_visible_size;
121        };
122    };
123};
124
125struct drm_i915_query_memory_regions {
126    __u32 num_regions;
127    __u32 rsvd[3];
128    struct drm_i915_memory_region_info regions[];
129};